As high speed serial data rates advance from 15 Gb/s to beyond 50 Gb/s, we face a fundamental shift. Conventional logic-emulating NRZ (Non-Return to-Zero) signaling is being replaced by PAM4, a 4-level pulse amplitude modulation scheme that takes half the bandwidth to transmit the same payload as the equivalent NRZ signal. PAM4 challenges signal integrity, test, and design engineers who are responsible for SERDES (serializer/deserializer) components, interconnects, backplanes, cables, connectors, circuits, and complete systems.
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